From 6445e2974dd46aea5be697e23567a5b76d86bade Mon Sep 17 00:00:00 2001
From: Saku Rantamäki
Date: Wed, 13 Jun 2012 01:05:31 +0300
Subject: verilator 3.833

Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus
some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It
is designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.

Closes #12798.

Signed-off-by: Adam Vandenberg <flangy@gmail.com>
---
 Library/Formula/verilator.rb | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 Library/Formula/verilator.rb

(limited to 'Library')

diff --git a/Library/Formula/verilator.rb b/Library/Formula/verilator.rb
new file mode 100644
index 000000000..66fbd4433
--- /dev/null
+++ b/Library/Formula/verilator.rb
@@ -0,0 +1,15 @@
+require 'formula'
+
+class Verilator < Formula
+  homepage 'http://www.veripool.org/wiki/verilator'
+  url 'http://www.veripool.org/ftp/verilator-3.833.tgz'
+  sha1 '4ca58d609371b0a6309c5564a5e8ba6857aa15db'
+
+  skip_clean 'bin' # Allows perl scripts to keep their executable flag
+
+  def install
+    system "./configure", "--prefix=#{prefix}"
+    system "make"
+    system "make install"
+  end
+end
-- 
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